1. Technical Field
The present invention relates to a PROM IC and, particularly, to such PROM IC capable of executing a margin test for memory state of respective memory cells of such as EPROM or EEPROM, etc., under severe conditions and capable of selecting reliable memory IC.
2. Prior Art
Non-volatile read-only memory includes mask read-only memory (ROM) which is not erasable and programmable read-only memory (PROM). PROM includes erasable programmable read-only memory (EPROM) and electrically erasable programmable read-only memory (EEPROM).
PROM can generally be classified into the fuse type which is writable only once, such type as FAMOS which is rewritable by avalanche breakdown after erase by ultraviolet ray and such type as MNOS which is electrically erasable/rewritable by tunnel effect. A PROM IC includes a matrix of memory cells of any of the above mentioned types constituting a memory array. A general construction of the PROM IC is shown in block in FIG. 3.
In FIG. 3, a memory cell array 1 is constituted with a plurality of memory cells 1a, 1b, . . . arranged in a column and row matrix.
A column decoder 2 is responsive to an address signal A indicating a column address A to select a column having an address A and a row decoder 4 is responsive to the signal A to select a row having an address A, so that one of the memory cells which is arranged in a position defined by the column address A and the row address A is selected.
A read voltage from a read voltage application circuit 3 is applied to the thus selected memory cell through the column decoder 2 and a read signal from the selected memory cell corresponding to an information written in the memory cell is amplified by one of sense circuits 5a, 5b, . . . corresponding thereto to provide a binary one value. An output of the sense amplifier is inverted to the other value in response to an input voltage exceeding a predetermined threshold value.
The read voltage application circuit 3 is responsive to a test selection signal T to switch the read voltage to be applied to any of the memory cells through the column decoder 2 from a standard read voltage S to an external application voltage E. An operational relation among the read voltage application circuit 3, the memory cell and one of the sense circuits and hence sense amplifiers SA thereof corresponding thereto (in this example, sense circuit 5c) will be described with reference to FIG. 4. It should be noted that the test signal T is produced correspondingly to a signal externally set for selection of test state.
In FIG. 4, it is assumed that a memory cell 1c of the PROM IC is selected by the address signal supplied to the column address decoder 2 and the row decoder 4. For clarification of illustration, other memory cells are omitted and the column decoder 2 and the row decoder 4 are shown by mere dotted lines respectively. Since, in this example, the memory cell 1c is composed of a floating type transistor Qc, the read voltage is applied through the column decoder 2 to a gate electrode of the transistor Qc.
With absence of test selection signal T, that is, during a normal read, the transistor Qb of the read voltage application circuit 3 is in "OFF" state. Therefore, a predetermined standard read voltage S is applied by the read voltage application circuit 3 to the gate electrode of the transistor Qc. On the other hand, when a test selection signal T is supplied externally, that is, a performance test such as marginal test is to be performed, the transistor Qb is turned "ON" and the external application voltage E is supplied through a test terminal of a PROM IC or any other external terminal to the gate electrode of the transistor Qc of the memory cell 1c as a read voltage to read a stored information. For test, a storing state of the memory cell 1c, that is, a capturing state of electrons or holes at the floating gate of the transistor Qc is detected by the sense circuit 5c connected through the row decoder 4 to a drain electrode of the transistor Qc. The detection is performed by applying a predetermined reading voltage to the gate electrode of the transistor Qc and detecting a current drive capability of the transistor Qc.
Describing this in more detail, an input of the sense amplifier SA of the sense circuit 5c is connected to the drain of the transistor Qc and its potential is pulled-up by a source voltage Vcc through a resistor R1 whose value is several hundreds K ohms to several M ohms usually. Therefore, when the predetermined reading voltage is applied to the gate of the transistor Qc, a read current whose value corresponds to the read voltage flows from the source Vcc to the transistor Qc. With this current flow, a corresponding voltage drop occurs across the resistor R1, which is used as a read signal. The read signal is amplified by the sense amplifier SA and binarized thereby according to the voltage value thereof. The binarized output of the sense amplifier SA is supplied from the IC externally.
On the other hand, a threshold voltage of a floating type transistor at which the latter transistor is "ON"/"OFF" operated is determined by the degree of capture of electron or hole at the floating gate. Further, when the read voltage is higher than the threshold value, the transistor is turned "ON" and, when lower, it is turned "OFF". Therefore, it is possible to obtain a state in which a normal value written in the memory cell is output, correspondingly to the voltage value applied to the gate of the same transistor and thus to detect the storing state of the same memory cell.
In order to test the written state of the selected memory cell, that is, in order to test the degree of capture of electron or hole at the floating gate of the transistor Qc, the read voltage is switched from the standard read voltage S to the externally applied voltage E which may be lower than the standard read voltage, with which the written state of the selected memory cell is detected as a binary output thereof.
Thus, by reading the information written in the memory cell by means of the externally supplied read voltage E, it is possible to perform a marginal test for an actual read condition and to thereby supply only PROM IC's whose performance is more stable as products.
There may be a case where a sufficient marginal test is impossible, dependent upon the type of the memory cell. In detail, in the floating gate type transistor as the memory cell, when the floating gate captures holes or discharge electrons to make the transistor of depletion type, the marginal test is impossible. That is, in order to perform a marginal test when the transistor forming the memory cell becomes depletion type, the externally applied read voltage E must be set to a negative value possibly as low as -4 V. With such negative read voltage, a terminal for applying the external application voltage E or a path extending therefrom to a transistor of a selected memory cell of the floating type transistor memory is short-circuited to a ground terminal due to an effect of a parasitic diode existing in a portion of the path, making the performance test impossible.
Therefore, in the past, it has been practically impossible to perform a sufficient test of a memory unless such marginal test is performed for a wafer having only a circuit dedicated to such test or for memories which are subjected to destructive test. So far, marginal test of mass-produced PROM IC's is performed by applying external application voltage of 0 V at most and therefore reliability of such PROM IC's is not enough.